1. Field of the Invention
The present invention relates to semiconductor integrated circuits such as a DRAM (Dynamic Random Access Memory), and more particularly to a semiconductor integrated circuit which can be set to a test mode for a manufacturing test.
Priority is claimed on Japanese Patent Application No. 2008-116331, filed Apr. 25, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, in the field of manufacturing tests which test functions and operations of semiconductor integrated circuits such as a DRAM, attention has been drawn to the technique in which a plurality of semiconductor chips, which are subjects of manufacturing tests, are connected to a test system or a tester and these semiconductor chips are tested in parallel, to achieve efficiency of the test and shortening the time required for the test.
As an example of such a technique, a method is proposed for reducing the number of input terminals which are used in the manufacturing test of a semiconductor storage apparatus to input an address (Japanese Unexamined Patent Application, First Publication No. H11-306796 (hereinafter referred to as “Patent Document 1”)). In accordance with this proposed method, in a normal operation, an address is read once per two periods of a clock ICLK in response to one of two rising edges in the two periods (i.e., in response to every rising edge of a thinned out clock). In contrast, in a manufacturing test, the clock ICLK is not thinned out, and addresses are read in response to every rising edge of the clock. Therefore, in the manufacturing test, addresses are read in accordance with a clock having a rate double the rate of a clock used in the normal operation. As a result, addresses can be input through half the number of address input terminals in accordance with a time-division multiplexing scheme.
However, the present inventor has recognized the following matters.
The method proposed by Patent Document 1 halves the number of address input terminals used in a manufacturing test. However, this proposed method is incapable of inputting signals such as a clock enable signal, a chip select signal, a row address strobe signal, a column address strobe signal, or a write enable signal, which are signals input through control terminals other than the address input terminals, in accordance with the time-division multiplexing scheme.
This is because in order to set a semiconductor storage apparatus, which is the subject of manufacturing tests, to a test mode, it is necessary to set up a mode register provided in the semiconductor storage apparatus by setting the chip select signal, the row address strobe signal, the column address strobe signal, and the write enable signal to a predetermined level (e.g., a low level) and by subsequently inputting a clock signal to the semiconductor storage apparatus.
Therefore, there is a problem in that it is not possible for the method proposed by Patent Document 1 to reduce the number of control terminals used in the manufacturing test.